The present invention relates generally to a semiconductor memory device and a refresh method thereof, and more particularly, to a semiconductor memory device configured to write data simultaneously in a plurality of cells without increasing a write current.
Recently, the demand for semiconductor devices has increased due to the rapid distribution of computers. These semiconductor devices are required to operate at high-speed with high accumulating capacity. As a result, various manufacturing techniques have been developed to improve the integration, response speed, and reliability of the semiconductor devices.
Dynamic Random Access Memory (DRAM), configured to input and output information freely at high capacity, has been widely used in semiconductor devices. The DRAM includes a memory cell region, for storing information data with a charge type, and a peripheral region, for inputting and outputting the information data. The DRAM also includes an access transistor and an accumulating capacitor.
The DRAM must have a continuous power supply in order to store data as a volatile memory. Instant disconnection of the power may destroy the data of a RAM because a memory cell of the DRAM is designed based on small charging electrons for maintaining the charged power. These charging electrons are analogous to a tiny battery that is not continuously recharged, and which may therefore lose even the previously charged power.
A refresh operation refers to a recharging process of a memory cell in a memory chip. Memory cells in a row may be charged in each refresh cycle. Although the refresh operation is performed by the system's memory control, some chips are designed to perform a self-refresh operation.
For example, a DRAM chip having a self-refresh circuit configured to perform a self-refresh operation without a Central Processing Unit (CPU) or an external refresh circuit has been disclosed. The self-refresh method has been frequently used in portable computers to reduce power consumption.
FIG. 1 is a diagram showing a cell array of a conventional DRAM.
The conventional DRAM comprises a plurality of bit lines BL arranged in a column direction and a plurality of word lines WL arranged in a row direction. A plurality of unit cells are positioned at the intersections of the word lines WL and the bit lines BL.
Each unit cell performs a switching operation depending on the state of the word line WL, and includes one switching element T, for connecting a capacitor C to the bit line BL, and one capacitor C, connected between a plate line PL and a terminal of the switching element T. The switching element T includes an NMOS transistor, and the switching operation of the switching element T is controlled by a gate control signal.
A sense amplifier S/A, connected to the bit line BL, senses and amplifies cell data applied from the bit line BL. The sense amplifier S/A is shared by two bit lines BL.
The DRAM stores charges in the capacitor C and senses a change in the voltage applied to the sense amplifier through the bit line BL to distinguish a logic data “1” from a logic data “0”. The capacitor C requires capacitance of a few fF because the DRAM is required to read fine changes in voltage of the bit line BL.
However, the conventional DRAM must frequently perform the refresh operation because it is volatile and has a short refresh cycle. That is, in the conventional DRAM, charges stored in the capacitor C leak over time. As a result, the DRAM cyclically performs a refresh operation for reading and writing data (for example, every 64 msec), which causes large power consumption and degradation of operational performance.
Generally, a nonvolatile memory, such as a magnetic memory and a phase change memory (PCM), has a data processing speed similar to that of a volatile Random Access Memory (RAM), and can conserve data even after the power is turned off.
FIGS. 2a and 2b are diagrams showing a conventional phase change resistor (PCR) 4.
The PCR 4 comprises a phase change material (PCM) 2 inserted between an upper electrode 1 and a lower electrode 3. Application of a voltage and a current to the PCR 4 causes such an increase in temperature in the PCM 2 that the electrically conductive state of the PCR 4 is changed depending on resistance.
The PCM 2 comprises AgLnSbTe. The PCM 2 may also comprise chalcogenide having chalcogen elements (S, Se, Te) as a main ingredient, specifically a germanium antimonic tellurium (Ge2Sb2Te5) consisting of Ge—Sb—Te.
FIGS. 3a and 3b are diagrams illustrating operation of the conventional phase change resistor shown in FIGS. 2a and 2b. 
As shown in FIG. 3a, the PCM 2 may be crystallized when a low current, i.e., a current less than the threshold value, flows through the PCR 4. As a result, the PCM 2 becomes a crystallized low resistance material.
As shown in FIG. 3b, the PCM 2 can be amorphized when a high current, i.e., a current higher than a threshold value, flows through the PCR 4. That is, the temperature of the PCM 2 is increased higher that its melting point when a high current flows through the PCR 4. As a result, the PCM 2 becomes an amorphous high resistance material.
In this way, the PCR 4 is configured to store nonvolatile data corresponding to the two resistance states. A logic data “1” refers to the PCR 4 having a low resistance state, and a logic data “0” refers to the PCR 4 having a high resistance state, such that the logic states of the two data can be stored.
FIG. 4 is a diagram illustrating the write operation of a conventional phase change resistance cell.
Heat is generated when a current flows through the upper electrode 1 and the lower electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 is changed to be either crystalline or amorphous depending on temperature given to the upper electrode 1 and the lower electrode 3.
When a low current flows for a given time, the PCM 2 becomes crystalline and the PCR 4, having a low resistance, is at a set state. On the other hand, when a high current flows for a given time, the PCM 2 becomes amorphous and the PCR 4, having a high resistance, is at a reset state. The difference between the two phases corresponds to a change in the electric resistance.
As a result, a low voltage must be applied to the PCR 4 for a longer period of time in order to write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a shorter period of time in order to write the reset state in the write mode.
However, a phase change memory device using the PCR 4 has a large write current for writing data in a cell. As such, the number of cells to which date can be written simultaneously is limited resulting in degraded write performance.
Although the conventional phase change memory device has a nonvolatile characteristic, cell data is subject to increasing degradation over time, thereby limiting data retention time.
When current of the bit line BL corresponding to the logic data “1” and “0” is decreased, the data retention characteristic is degraded, resulting in difficulties in retaining the optimum nonvolatile cell storing characteristic for a long period of time.
A magnetoresistive random access memory (MRAM) is a memory device that utilizes multi-layer ferromagnetic thin films. The MRAM reads and writes data by sensing current variations according to the magnetization direction of the respective thin films.
That is, the MRAM as a memory type for storing a magnetic polarization state in a magnetic material thin film changes or senses the magnetic polarization state by a magnetic field generated by combination of a bit line current and a word line current so as to read and write data. The MRAM has a high speed and low power consumption. The unique properties of the MRAM's magnetic thin film allow for high integration density. The MRAM also performs nonvolatile memory operations, such as a flash memory.
Generally, the MRAM includes various kinds of cells such as Giant Magneto Resistance (GMR) cells and Magnetic Tunnel Junction (MTJ) cells. The MRAM embodies a memory device by using the GMR or spin-polarized magneto-transmission (SPMT) phenomenon generated when the spin influences electron transmission.
In implementing a GMR magnetic memory device, the MRAM, using the GMR phenomenon, utilizes the fact that resistance remarkably varies when spin directions differ in two magnetic layers having a non-magnetic layer there between. In implementing a magnetic permeable junction memory device, the MRAM using the SPMT phenomenon utilizes the fact that larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer there between.
FIGS. 5a and 5b are diagrams illustrating the cell array of a conventional MRAM. FIGS. 5a and 5b show a MRAM configured to read/write data using a spin transfer torque system.
A conventional MTJ cell has a deposition structure including a fixed magnetic layer 5, a tunnel junction layer 6, and a free magnetic layer 7. The free magnetic layer 7 and the fixed magnetic layer 5 are made of a material such as NiFeCo/CoFe, and the tunnel junction layer 6 is made of a material such as Al2O3.
The free magnetic layer 7 has a different thickness from that of the fixed magnetic layer 5. The fixed magnetic layer 5 has a magnetic polarization state which is changed in a strong magnetic field, and the free magnetic layer 7 has a magnetic polarization state changed in a week magnetic field.
A transistor T connected between the MTJ cell and a source line SL is controlled by a word line WL. The bit line BL is connected to the free magnetic layer 7 of the MTJ cell, and the fixed magnetic layer 5 is connected to the drain of the cell switching transistor T. The source line SL is connected to the source of the cell switching transistor T.
A voltage generator 8 is connected to both the bit line BL and is the source line SL and supplies a bipolar write pulse and a read bias for applying write/read voltages. A sense amplifier SA senses and amplifies the voltage of the bit line BL based on the reference voltage received from a reference voltage generating unit 9.
FIGS. 6a and 6b are graphs illustrating current and resistance fluctuation curves based on voltage of the conventional MRAM.
When a high voltage is applied to the source line SL and a low voltage is applied to the bit line BL, a logic data “1” having a high resistive state is written in the MTJ cell. When a low voltage is applied to the source line SL and a high voltage is applied to the bit line BL, a logic data “0” having a low resistive state is written in the MTJ cell.
However, the MRAM using a MTJ cell requires a large write current for writing data in the cell. As a result, the number of cells to which data can be written simultaneously is limited resulting in degraded write performance.
A resistive random access memory (ReRAM) device is a nonvolatile memory device which applies external voltage to thin films to change the electric resistance of a material, thereby using the resistance difference to denote a binary on/off.
FIG. 7 are diagrams showing a resistive switch device (RSD) of a conventional ReRAM.
The RSD includes a resistance switch 11 disposed between an upper electrode 10 and a lower electrode 12. The upper electrode 10 and the lower electrode 12 include a metal material, such as platinum (Pt), and the resistance switch 11 includes a resistance insulating layer, such as TiOx.
Studies have focused on the ReRAM since the 1960s. Generally, the ReRAM includes a metal-insulator-metal (MIM) structure using a metal oxide. As a result, if a proper electrical signal is applied, the memory characteristic of the ReRAM changes from a state in which the resistance increases and the material is not conductive (off state) to a state in which the resistance decreases and the material is conductive (on state).
The ReRAM includes a current controlled negative differential resistance or a voltage controlled negative differential resistance depending on the electrical method for embodying on/off characteristics.
Materials that display a ReRAM characteristic are categorized as follows: materials such as colossal magneto-resistance (CMR) and Pr1-xCaMnO3 (PCMO), which are inserted between electrodes to use resistance change by an electric field; binary oxides such as Nb2O5, TiO2, NiO, Al2O3, which have a nonstoichiometric composition and are used as a resistance change material; a chalcogenide material, which is kept amorphous without any phase changes by flowing a high current like a phase change random access memory (PRAM) so as to use a resistance change resulting from a change of the threshold voltage of an ovonic switch; materials SrTiO3 and SrZrO3 doped with Cr or Nb to change a resistance state; and programmable metallization cells, created by doping Ag having large ion mobility on solid electrolytes such as GeSe to have two resistance states depending on formation of a conductive channel in a medium by electrochemical reaction. Through embodiment of two resistance states, such materials having a memory characteristic or process methods have been reported.
FIG. 8 is a graph showing a current-voltage relation of the conventional ReRAM in a DC sweep mode.
An electric forming step is required to show memory movement of the ReRAM. A ReRAM material with a switching electrical characteristic is changed from a high resistance state to a low resistance state by the electric formation.
In case of binary oxides, as the voltage applied to the device is increased after the electric forming step, the current follows the curve (a) of the low resistance state (Low R). When the voltage applied to the device reaches a critical value, the current shows a negative differential resistance as shown by (b).
As shown by curve (c), the current maintains the high resistance state (High R) to a given voltage, and when the voltage reaches a set voltage Vset, the current changes to the low resistance state (Low R) as shown in (d). When an electrical signal is a pulse a reset voltage Vreset and the set voltage Vset are applied to obtain the High R and the Low R.
The set voltage Vset, corresponding to an erase voltage Verase, has a higher voltage value than that of the reset voltage Vreset, corresponding to a write voltage Vwrite. A read voltage Vread has a lower voltage value than that of the reset voltage Vreset.
However, the ReRAM using the RSD requires a large write current for writing data in cells. As such, the number of cells to which data can be written simultaneously is limited resulting in degraded write performance.